Design Verification Engineer at Google. Currently working on IP/Subsystem level design verification of Silicon Security IPs. • Experience in IP level/Top level SoC Verification using Advanced Verification Methodologies(SV/UVM) • Experience of building Configurable Verification Environment and Components. • Good understanding of SystemVerilog OOPs concepts. • Experience in writing Assertions and Functional Coverage for Constrained Random Verification. • Experience in Analog Behavioral Modeling and Mixed signal Co-simulations. • Experience in analyzing top level SOC schematic, extracting netlist and running full chip DMS simulations. • Experience in Real Number Modelling and Model Validation against transistor level schematic. • Hands-on experience using DV simulation tools, Waveform and schematic tools.