A competent professional with total work experience of 7+ years in ASIC Design and Verification. The experience is broadly classified into the following categories: ✔️Expertise in verification methodologies like UVM, and hands on experience in building test benches/verification environment. ✔️Expertise in System Verilog, Verilog. ✔️Hands on experience Ethernet Protocol . ✔️Hands on experience and good understanding on protocols and IP like AHB lite, AMBA AHB, APB, SPI, I2C. ✔️Hands on experience in Integrating test benches and writing test cases. ✔️Possess good debugging skills. ✔️Hands on experience in System Verilog Assertions (SVA). ✔️Hands on experience writing Code/Functional coverage goals. ✔️Preparing Test Plan. ✔️Exposure of the GLS for the subsystem. ✔️Understanding the Python scripting language. ➕More Facts: 🔍Having good communication and problem solving skill. 🔍Ability to work in a dynamic environment. 🔍Believes in progressive learning and possess learning attitude. Contact Info:- E-mail_ID:-poojakumari91996@gmail.com