8+ years of experience in DFT. Passionate about defining the right test logic for the design to ensure the silicon quality. + Boundary Scan, Memory BIST and repair, Hybrid TK/LBIST, scan architectures and implementation + ISO26262 compliant DFT for automotive designs + Timing constraints development and closure for DFT modes + Pattern generation and verification through zero-delay and timing simulations + Silicon bring up using Silicon Insight and ATE support + Architectures : IEEE 1149.1, IEEE 1687 + Scripting skills in PERL, TCL, Shell + Powerful communication and presentation skills