> Hands-on experience in RTL Design and Micro-Arch. RTL coding using Verilog/VHDL/SV. > Hands-on experience in working with interface protocols like APB/AHB/AXI. > Hands-on Working Experience in Ethernet, UWB. > Working Experience in Spyglass Lint/CDC/RDC, Synthesis, LEC, ECO Flows, simulation debug tools(simvision/verdi), GLS & Power Analysis