• 19+ years of professional experience in Semiconductor Industry (VLSI) particularly in IO Circuit Design Domain • Experience in handling all aspects of project management right from o Making sales pitch for potential clients o Customer interface during technical engagement o Owning up complete responsibility for cost/efforts estimation, coming up with CAD requirement, PDK setup, Project Management, Execution and Delivery • IO circuit Design o Hands-On experience in IO cells design of I2C, DDR2/3, LVDS, LVCMOS, Failsafe IOs, Over Voltage Tolerant IOs HS Receiver for MPHY/HDMI, SERDES, Bias Generator, Termination Calibration In technology: 28nm,40nm,65nm,130nm, 180nm, Well-versed with challenges of Finfet Design o Lead IO library development in 28nm which are silicon-proven which included LVCMOS IO, Open drain IOs, Analog pads o Developed 28 nm LVDS Receiver 1.8-volt architecture with low offset working up 2GBPS proven on Silicon o Developed 40nm,28 nm 3.3 v overvoltage IO library with 1.8V devices proven on silicon o 65nm,180nm BCD IO library for low leakage requirement for hearing aid application proven on Silicon o 130nm LVDS Receiver working up to 1.6Gbps o USB1.1 IO Cells in 180nm Flash process o Termination calibration for DDR, HDMI/DP, MPHY, USB • PHY Design and Verification o Lead porting of AFE of 28nm FDSOI HMDI/DP receiver IP, 28nm FDSOI MPHY Receiver IP, 28nm SMIC MPHY Transceiver AFE IP • Analog Layout Experience o Layout of integrator for sigma-delta ADC, with critical matching and parasitic sensitive constraints in 45nm technology, Reference bias generator for the USB in 40nm o Layout tweaks for CSI interface in 65nm (ESD and performance enhancement) • Analog Verification Experience o Worked with TI for top-level analog verification of Wireless IP