About me

I’m an RTL & ASIC Design Engineer with 9+ years of experience in developing production-grade IPs for camera, memory, and NoC subsystems. At Qualcomm, I contributed to Meta’s Ray-Ban Smart Glasses and implemented DisplayPort over USB-C Alternate Mode, covering both Source and Sink roles. My core strengths include RTL Design, Microarchitecture Planning, Synthesis Readiness, Area Optimization, and CDC/RDC closure. I’ve driven IPs from spec to silicon, including parameterized datapath units and complex camera subsystems. I also bring hands-on experience with FPGA to ASIC migration, having designed high-performance RTL blocks that scale well across platforms. My deliverables have spanned clock and reset control, memory integration with repair flows, power sequencing, and design bring-up support. As a mentor, I help candidates understand how to align their resumes, projects, and interview preparation with what ASIC hiring managers actually look for. I guide engineers in bridging the gap between academic exposure and real industry expectations.