I’m Nikhitha Chevala, a dedicated professional with hands-on experience in Design for Testability (DFT) engineering and a strong background in VLSI design. Currently working at AMD. I specialize in SOC-level ATPG, scan chain tracing, coverage improvement, and timing simulations for advanced automobile chip projects. My academic foundation, with an M.Tech in VLSI Design from NIT Karnataka, has equipped me with a robust understanding of digital electronics and hardware languages like Verilog. I’m passionate about collaborating with professionals in the semiconductor industry and mentoring students or new graduates eager to enter the VLSI domain. Whether it's navigating technical challenges or sharing career guidance, I aim to provide insights that help build a solid foundation in DFT and SOC design. I’m also interested in engaging with professionals on open-source projects or innovative collaborations that advance the boundaries of chip design and testability. Let’s connect to discuss opportunities, share knowledge, and drive impactful projects together.