I am a SoC RTL Design Engineer with 7+ years of industry experience, currently working as a Senior Design Engineer in one of the product company in Barcelona, Spain. My work has primarily focused on RTL design, subsystem integration, and design sign-off for large-scale ASIC SoCs. I have hands-on experience working on multiple production tape-outs across advanced technology nodes (5nm, 4nm, 10nm, 14nm), collaborating closely with Design Verification and Physical Design teams. My background includes working on automotive, mobile, AI accelerator, and wearable SoC projects. Technically, I have deep experience in: RTL design and subsystem-level integration Integration of peripheral and system IPs such as PCIe, UFS, UART, I2C, SPI, GPIO, PADs, CMU, PMU Design sanity checks: compile, lint, CDC, RDC, DFT, low-power checks Debugging complex RTL issues using Synopsys Verdi Writing SDC constraints and supporting synthesis and GLS Working with AMBA protocols (AXI, APB, AHB) and low-power concepts (UPF, Q-channel) Having mentored junior engineers and worked closely with cross-functional teams, I understand both what interviewers expect and what real RTL design roles demand on the job. Through my sessions, I aim to help engineers: Build strong RTL fundamentals with real-world context Prepare effectively for RTL design interviews Understand SoC integration workflows and expectations Identify gaps and grow confidently as RTL engineers If you are preparing for an RTL design role or want practical guidance from someone working on real silicon, my sessions are designed to be clear, structured, and industry-focused.