✅ Core Verification Expertise IP and Subsystem-level verification & test plan development Constrained-random verification, assertions, and coverage-driven verification Developing checkers, reference models, and debugging complex failures Coverage improvements, profiling, and optimization of test environments Team leadership as well as individual technical contributions ✅ Protocols & Technology Experience High-Speed Protocols: Ethernet (up to 100Gbps), RGMII, GMII, Ethernet PCS 1.6Tbps, PCIe Gen4 EP, OSPI Bus Protocols: AXI4, AXI3, APB Security Protocols: IPsec, TCP/IP, PKI (RSA, ECDH, ECDSA) Low-Speed Interfaces: UART, SPI, I²C Serial Interfaces: RS232, RS422, RS485 ✅ Tools & Platforms Simulation Tools: Questasim, Synopsys VCS, Cadence Xcelium, Verdi, Visualizer SoC/FPGA Tools: Libero IDE, LiberoSoC, Xilinx Vivado Scripting & Automation: Python, Perl Hardware Verification: Xilinx-based subsystems ✅ Silicon Validation & Hardware Design Experience (Early Career – 4 Years) Hands-on experience with uC, uP, CPLD, ARM Cortex-M3/M4, FPGA, and SoC FPGA Worked on memory controllers: EEPROM, NOR/NAND Flash, DDR3L Interfaces & protocols: UART, SPI, I²C, QSPI, OSPI, USB2.0, USB3.0 Type-C, RGMII Knowledge of Signal Integrity, EMI/EMC guidelines, and product design life cycle Experience in DC-DC regulator design and selection as per system requirements