Senior ASIC Design and Verification Engineer at NVIDIA. Expertise includes: In-System Testing for Automotive DFT Test Access Mechanism using Hi-Speed IO's DFX DV - Verification Methodology, Infrastructure Development, Project Execution Post Silicon Bringup and Productization for High-Speed Test-Access IEEE1500/IEEE1687 JTAG RTL insertion, NA, Timing closure, and verification DFX on FPGA - Bringing up DFT features on FPGA for early SW development DFX on Emulator - Bringup safety critical DFT features on Emulator for gate level coverage and extensive pattern checkout