An Engineer with broad skill-sets and over 10 years of experience in ASIC and FPGA Design: - Proven experience in SoC Development - Proven experience in FPGA Fast prototyping, validation and qualification for production - Experienced in Power analysis and power reduction for DSP and Image processing chips - Handled responsibilites from Architecture to RTL to Sign-off, Performance/Power/Area (PPA) trade-offs - Have helped integrate new team mates and get up to speed with work flow - Experienced in IP Design/Development, Verification, Validation at Lab and QC process - Architecture and Design experience in sub-system and block level (Aerospace and Defense projects) for 3 years. - Experienced in Static Timing Analysis (STA), Clock Domain Crossings (CDC), Floor Planning, Memory placements and Formal verification using Formalty. - Established Work flow improvements and Optimizations for STA flow - Knowledge of design flow for ASIC and FPGAs and Verification methodologies - Knowledge of Design Space Exploration, High level synthesis and SystemC TLM. - Have worked on Digital implementation of algorithms and Digital front-end of RF systems - Certification and experience with RISC-V CPU design and Free RTOS - Knowledge and Certification with Machine learning and Deep learning basics - Proficient in end to end flow for Xilinx and Altera FPGAs - Languages : VHDL, Verilog, SystemVerilog, SystemC/TLM, C, C++, Python, Tcl, Perl - Tools: Synopsys Design Compiler/PrimeTime/SpyGlass, Cadence Design Tools - Virtuso, Encounter, Incisive , ModelSim, Synplify Pro, NCLaunch, Xilinx Vivado Suite, Altera Quartus, Visual Studio - Have worked with SerialRapidIO, Aurora, SPI, UART, I2C and other digital high speed interfaces - Good knowledge of Embedded systems (board and system level), debugging and boot-up of prototypes acquired through industrial experience - Has experience in testing at lab for RF sub-systems, Board initial bring up, etc - Cross-team co-operation to reach overall goals - Enthusiastic about learning new technologies