- Good Understanding of SV,UVM verification flow. - Exposure to Design verification tools. - Knowledge in UVM , ability to code independently using SV-UVM methodology as a part of test sequences - Experience in using industry standard EDA tools for the front-end design and verification - Knowledge on AMBA protocols ( APB,AXI). -Theoritical Knowledge on PCIE Protocol. VLSI DOMAIN SKILLS HDL: Verilog HVL: System Verilog Verification Methodologies: Coverage Driven Verification TB Methodology: UVM Tool: Synopsys VCS.