EDUCATION Bachelor of Technology (Electronics and Instrumentation) | 2014 – 2018 VIT University, Vellore PROFESSIONAL EXPERIENCE Currently working at Google as Silicon CAD Engineer ● CDC/RDC Methodology Lead: Developed and deployed a robust RDC sign-off methodology, resulting in the early detection of a critical bug (ECO), preventing major downstream silicon issues. ● Strategic Tool Migration: Successfully led the high-risk migration from SG-CDC to VC-CDC for 25 subsystems, ensuring violation comparability and runtime stability during high-pressure milestones. ● Component IP Support: Enabled first-time CDC/RDC implementation for various IP configurations using VC Spyglass and deployed configurable waivers to streamline the process. ● Flow Triage & Support: Act as primary POC and "first-level triage" for critical static-check flows including VCLP, LEC, and Synthesis during project milestones. ● Technical Innovation: Piloting Meridian RDC and VC-CDC Assertion flows to evaluate tool capabilities against evolving design requirements and sign-off strategies. ● Training & Mentorship: Conducts targeted training sessions and debug "office hours" for designers; mentors junior members and XWF teams on CDC flow adoption. Intel India | SoC Design Engineer | 2018 – 2023 ● Subsystem Ownership: Single-handedly built the Memory subsystem design database from scratch in a new environment and developed the APB decoder module for glue logic. ● RDC/CDC Sign-off: Held complete ownership of Spyglass RDC check setups and delivered high-quality CDC results for 6nm and 7nm inferencing products. ● Design Quality: Led design reviews for Connectivity, Spyglass OpenLatch, and Lint (Flat/NRF), ensuring all critical milestones were met with zero opens. ● Post-Silicon Readiness: Supported FE-to-BE handoff for DDRPHY IP and implemented post-RTL freeze ECOs. Intel India | SoC Design Intern | 01/2018 – 07/2018 ● IP Integration: Gained expertise in DDR protocols and the integration of generic and in-house IPs into mobility device SoCs. ● Quality Checks: Supported front-end quality checks including Lint, CDC, and UPF. TECHNICAL SKILLS ● EDA Tools: CDC (VC Spyglass CDC, Questa, Spyglass), RDC Analysis (VC Spyglass RDC, Meridian RDC), Lint, VCLP, LEC, Synthesis, CoreConsultant. ● Automation & Scripting: Tcl (Advanced), Make, Perl, Python (Basics), Shell Scripting. ● Design & Hardware: Verilog, System Verilog, RTL Integration, APB Protocols, DDR ● Methodologies: SDC Constraints, UPF, ECO flows, DFT_CDC. PUBLICATIONS & CONFERENCES ● DAC 2025: Selected for paper presentation on RDC Methodology; awarded Best Presentation in session. ● SNUG India 2024: Presented technical paper on RDC flows and sign-off. ● Co-Author: "SoC Custom Register Framework" (Automated register collateral generation). ● Co-Author: "DFI Snooping Logic" (DDR IP debug and isolation).