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About me
Proficient in SystemVerilog, Verilog and UVM with a deep understanding of constrained-random verification, functional coverage and debugging at scale. Led verification teams, driven milestone closures and consistently delivered high-quality silicon validation across IP and SoC domains.
Let’s connect if you’re building next-gen silicon in networking, modem, debug,or interconnect-heavy SoCs and looking for experienced leadership in functional verification.
SV_UVM series package running on a discount! Go grab it
