I’m a passionate SoC & GPU Verification Engineer with 5+ years of experience in block-level and SoC-level verification, having worked on real-world silicon for Mobile, Automotive, TV, Wearable, and now Server-class AI chip markets. Currently at AMD India as a Senior Silicon Design Engineer, I have been working on a multi-chiplet AI server SoC project — verifying reset functionality across all chiplets for multiple partition modes in a complex SoC environment. Used existing DPI calls to drive transactions via C-based sequences in a C-UVM mixed environment. Collaborated with cross-functional teams to debug reset issues, analyze waveform behavior, and ensure robust bring-up flows. 🔧 Verification Expertise • Multi-chiplet AI SoC reset and partition mode verification • SoC-level GPU verification including Video Codec & Multimedia IPs • Environment bring-up, protocol/IP validation, attribute configuration • Testbench development, register tests, connectivity, & low-power simulations • CDC, GLS, X-Prop, and UPF-based simulations 🛠 Tools & Methodologies • Languages: SystemVerilog, Verilog, UVM, C, Python, Perl • Simulation/Debug: Xcelium, Verdi, SimVision, vManager, Verisium • Coverage: Functional & Code coverage closure • Known for: Ownership mindset, deep debugging, and quality-first delivery ⚙️ Automation, Scripting & GUI Tooling I believe in scaling productivity through automation. Some tools I’ve built: • Perl-based automation for testcase generation, VSIFs, and coverage configuration • A generic coverage framework to handle complex combinations efficiently • Regression dashboard to auto-track pass/fail/rerun stats in real-time • Python GUI Tools: – Coverage Generator: Engineers select cover points/bins via dropdown → SV code auto-generated & environment-ready – Register Testcase Creator: Builds register validation sequences from minimal input — fast-tracking regmap checks 🤖 Machine Learning Meets Verification Developed an NLP-based NER model to extract design entities from unstructured SoC specs — enabling auto-generation of verification scenarios. A step toward intelligent, ML-driven verification. 💡 Always building, always optimizing — I thrive on making verification faster, smarter, and scalable. 📩 Open to opportunities in DV roles where SystemVerilog, UVM, Python, and innovation meet. 📢 Also a Semiconductor Influencer — open for collaborations, partnerships, and knowledge-sharing opportunities.