Hands on Experience - Lead Front end activities. Two role : 1st RTL Design Er as an IC to deliver FE collaterals ( CDC, Synthesis), 2nd Mentor and Ramp up - Junior members and worked as a CoE Lead for INTEL(Center of Excellence Lead Hiring contractors and Guiding) Quora page : https://www.quora.com/profile/Kumar-Nandan-1 Experienced in : 1. Front end collaterals delivery to SD Team. 2. LEC signoff , worked on Global clock network. and Support Conformal and DC/FC flows for Synthesis. 3. Comprehensive knowledge on all Frontend flows. 4. 2012 - 2017 : worked on Design Verification Engineer profile for SoC projects. 5. 2018 - 2023 [ in continuation ] - SoC RTL Design Engineer role. Recent work experience : RTL Design Expertise : [ INTEL ] - worked on PCIe Phy layer and Link Layer Design - Verilog design, synthesis and simulation. - worked on Synthesis flow/LEC/Caliber/STA) , CDC, lint and Fishtail. - RTL checks and flows to maintain the health of SOC Design to deliver BE Team for Synthesis, Caliber. - Expertise in delivering FE collaterals : Synthesis activities : Handover RTL to SD for Intel Xeon Server. - LEC, DC/FC Fusion compiler Synthesis, Caliber, Fishtail [3yr] - Worked - PCI-e Gen 4 SoC for Server projects. Worked on Denali VIP and Resolved many issue. - Worked on EFFM Emulation with Model Bring up Exp. Past Work Ex: [ SoC DV ] + PCIE verification : Server projects [2] + Strong hands on experience NAND memories, SATA, PCIe, Coverage and Emulation . [5yr] + Qualcomm : Vectors, Code/Functional coverage, SDF & Timing Debug, ATE Vector. + Test vector development. + Debugging experience in Pre and post silicon failures. Worked with Testers. + Done Super macro verification - for Router projects in BROADCOM + BROADCOM : Functional, Innologic, ESPCV verification for TCAM, SCAN chain + NAND memories verification for SD. Education: + MDP Program : recently selected for IIM Kozhikode. [ 2022 batch] + CDAC qualified : 95.99%tile , PG in VLSI Design from CDAC ACTS RND Pune. [2012 batch] + B.Tech in ECE - 82.96% 1st rank in RGPV, MP. Holding 2 strong skills : 1. Engineer with mentorship qualities handling skills. 2. Mentor and guide people reaching offline and create an ecosystem which will bridge the gap between Industry and folks searching for opportunities. Handled - SOC verification, NAND verification, TCAM , LEC , PCIe verification, further moved into Server SOC RTL Design, clocks , FEBE Leading, Synthesis, Timing constraints. Worked on Global clock distributions. Last, I love to do photography from =~7yrs.