--scan architecture analysis. --Gone through coverage improvement by including shadow memory logic testable by different technique. --Lockup latch implementation for different clock domain. --Testpoint analysis implementation and flow. - Knowledge in fault modeling Stuck-at, Transition, Path Delay, IDDQ, and other advanced DFT models. - Experience in MBIST, Scan Insertion, ATPG, Fault Simulation and at-speed testing. xcelium - Experience with industry ATPG tools Synopsys Tetramax, and Mentor Dftadvisor Fastscan ATPG tool. --Gone through with scan synthesis flow, scan implementation, scan rule violation report generations and corresponding fixes for all violation. - Experience in Logic Design, VHDL, Verilog RTL and static timing analysis - Working knowledge in the following ; C, TCL and Perl. - Experience with industry simulation tools such as VCS, xcelium