Passionate about front end functional RTL Design and Verification. ☛ 12+ Years of Experience in IP & SoC Verification ☛ Expertise in IP Verification using SV and UVM ☛ Expertise in Developing Verification Environments Using Hardware Verification Languages ☛ Experience in Creating Verification Plans and Verification Objectives for SoC & IP ☛ Experience in SoC Verification based on Intel, ARM and ARC Processors ☛ Experience in Creation of SV - UVM- DPI based Environment for IP's & SoC's ☛ Expertise in Verifying PCIe , USB, HSIC, SSIC , Clock Generation Unit and System Power Control Unit ☛ Experience in Developing Firmware for HW-SW based co-simulations ☛ Experience in Debugging with Synopsys , Cadence and Questa Tools ☛ Expertise in Formal Verification using Jasper and Questa Formal ☛ Expertise in FPV using Jasper Gold and Questa Formal ☛ Experience in Verifying Power, Reset, Clock and FSM units using Assertions ☛ Experience in developing Low Power tests for PCIe and USB . Understanding of Low Power Concepts at SoC ☛ Version Control Tools : Clearcase , Git and SVN ☛ Skilled In: VHDL, Verilog, System Verilog, UVM, Specman, C, Perl , Shell , Tarmac, Clear case , git, SVN, Python,PCIe