-> Protocol knowledge of USB 3.0,USB 3.1, PIPE Spec -> Experience in Soc verification -> Having experience in chip , block and system level verification using SV and UVM methodology -> Developed all different VIP Components -> Exposure in all different simulator IUS, Questa, VCS -> Protocol knowledge of AXI, AHB , APB, SPI and exposure in USB 2.0 ->Languages known : System verilog , c ,c++ , UVM -> Experience of complete life cycle of project from the initiation to end -> Exposure in different scripting language : Perl,Python