22:T523,Work Experience: #AMD - Platform Architect #Apple - Performance Modeling engineer #Barefoot Networks (Intel) - Design Verification of network switch ASIC. #Intel- I interned at Intel in Summer 2019 in the post-silicon validation team for Gen 12 architecture. #Citigroup- Previously, I worked as an assistant manager- application developer -Java/C++. in Citigroup from June 2013 to July 2018 Education: #Masters in Computer Engineering (May 2020) at North Carolina State University. Coursework- - Advanced Microarchitecture, - Operating Systems Design, - ASIC and FPGA design with Verilog, - Microprocessor Architecture - Embedded Systems architecture, - GPGPUs : Advanced topics in computer architecture, - Internet Protocols - Quantum Computing Architecture, - UVM(Universal Verification Methodology) ASIC Verification, #B.Tech. in Instrumentation and Control (College of Engineering, Pune) Skills: #Architecture: Multilevel Cache, Pipelining, Branch Prediction, Instruction Level Parallelism, Out-of-Order Superscalar Pipeline, RISC-V, Bus Based Cache/ memory Coherence Protocols(MESI, MOESI), Memory Consistency #Languages: C++, JAVA, C, Python, OOPS, SystemVerilog, Verilog #ASIC Design: RTL Design, Synthesis, Logic Design, Asynchronous FIFO, Timing, FSM, Low Power Design, Clock Domain Crossing23:T496,

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Post-silicon Validation and Design Verification

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Kaustubh Jogalekar