GPU Physical Design Engineer at Qualcomm, where I work closely with the San Diego team on premium segment processors. My expertise spans across advanced technology nodes — including 2nm, 3nm, 5nm, and 7nm handling it from Netlist to GDSII, ensuring optimal performance, power efficiency, and reliability. I’ve had the opportunity to work on cutting-edge GPU and DPU architectures, where I specialize in resolving DRV violations, managing IR and crosstalk issues, optimizing clock distribution, and enhancing timing margins. My contributions have led to measurable improvements — including a 25% boost in design reliability, 20% reduction in pin count, and a 98% first-pass success rate in DRC and timing closure. I’m proficient with industry-standard tools like Synopsys ICC2, Fusion Compiler, PrimeTime, and Ansys Redhawk-SC, and I regularly automate flows using TCL and Perl scripting. My strength lies not just in technical execution, but also in collaborating with cross-functional teams to drive interface timing and design efficiency. I’ve also successfully cracked interviews at Google, Qualcomm, and Arrow, which has given me a deep understanding of what top-tier companies expect — both technically and behaviorally. I’m passionate about mentoring and helping others grow in the VLSI domain, especially in Physical Design.