I am the tech enthusiast and a quick learner. I am pursuing my career as DFT engineer. I have worked on multiple chips for Scan Insertion, test vector generation activities on block level as well top level. I am also involved in MBIST Insertion and simulation activity. Mentor: TestKompress(EDT), Tessent MBIST, Tessent Shell Synopsys: Design Compiler, DFTMax, TetraMax, Formality, VCS, Verdi, SpyGlass Cadence: NCSim, Conformal LEC, Simvision