I am Jay Maadam, an aspiring ASIC Physical Design professional with expertise in Verilog, TCL, PnR and Signoff. I have gained valuable experience in floor planning, placement, clock tree synthesis, and routing during my time in the field. I am passionate about driving innovation and making a meaningful impact on cutting-edge projects as a Physical Design Engineer. I am eager to connect with professionals in the industry and explore potential collaborations to unlock new possibilities and contribute to the advancement of ASIC Physical Design.