ASIC Design & Verification Engineer | VLSI | FPGA Specialist Embedded Systems Engineer with expertise in ASIC design, RTL verification, and FPGA implementation. Experienced in low-power design techniques and full chip design flow from RTL to GDS. - RTL Design & Verification (SystemVerilog, Verilog, VHDL) - ASIC Flow: Synthesis, STA, Power Optimization, DFT - Low-Power Design: Clock Gating, Power Gating, Multi-Vt - FPGA: Xilinx Vivado, Altera Quartus - RISC-V & ARM Architecture - Custom IP Core Development - Protocols: AXI, Avalon, UART, I2C, SPI - Tools: ModelSim, QuestaSim, PowerPro, Design Compiler Experience: Siemens EDA: developing low-power ASIC solutions for 28nm/11nm CMOS designs. Orange Maroc: challenge winner for IoT embedded systems. Proven track record in processor design, SoC integration, and verification.