Design Verification Engineer with strong hands-on expertise in Verilog, SystemVerilog, and UVM for functional verification of IP and SoC-level designs.
Experienced in architecting scalable, reusable UVM testbenches, developing directed and constrained-random tests, and implementing functional coverage and SystemVerilog assertions.
Focused on spec-driven, corner-case bug hunting, and coverage closure to ensure robust, production-ready silicon.
10% of earnings from these sessions will be donated to a social cause.
