STA Engineer at Intel India (Graphics). Currently working in the area of Timing and Quality sign-off and methodology. - Full-chip integration/timing sign-off - Timing constraints/exceptions handling/writing/validation - ETM/QTM lib generation/QA and IP-SOC interface timing sign-off - Working with SOC and RTL team on interface timing fixes - IP-IP interface timing sign-off using SNPS hyperscale methodology. - Block/section timing sign-off - repeater planning, timing model quality analysis, inter/intra timing violation analysis and fixes. - Led partition owners for ECO implementation - Handled tool/flows/methodology aspects of timing/variation/derating/PVTs - Knowledge on timing/STA/sythesis/implementation flows and checklist, QOR metrics - Quality sign-off methodology includes managing, qualifying different design rules related to RTL quality, timing, variation, connectivity, DRC (cap, tran) - Strong automation skills includes scripting related to flow enhancement, scripting for various repetitive QA tasks and for various custom reporting. - Trained interns/juniors on various topics of timing/quality sign-off Tools: Design Compiler, IC Compiler, Fusion Compiler and Prime-Time. Scripting: Perl and TCL