-Digital Design Verification Engineer with an extensive experience in IP /sub-system level over 6years -Proficient in verilog ,specman ,SV/UVM test bench methodologies and System verilog assertions. -In-depth knowledge of 3D NAND Memory design RTL ,firmware -knowledge on DDR3,CPRI and Onchip Peripheral Bus protocols -Tools: Synopsys vcs ,Verdi and Cadence Vmanager -version management -Clearcase and perforce