I have over all 7+ years of Experience. In that 4+ years of Experience on Constraints Validation And Support Role on Block Level to Top Level Convergence . I have Expertise on 7nm ,14nm, 45nm, 130nm and 180nm. At present I am dealing with STA (Full Chip Pre Static Timing Analysis/Block Level Pre Static Timing Analysis, Block Level/Top Level Check Timing Analysis, Unexpanded clocks Analysis, Timing Exceptions,GCA Violations Analysis,Clock Groups Reviews, Sign Off Checks, logs verification, getting constraints review from the IP teams, working with IP teams on constraints Feedback/ Reviews, Same source async Clocks Analysis, FCT Flat Runs , FCT HDM Runs ,FCT MV Runs, FCT partial runs, FCT run With SI, FCT run with Non-SI ,Constraints Development, No Clock Analysis, Unconstrained Endpoint Analysis, Timing Loops Analysis , Expert in bug finding...etc. I have a good knowledge on CADENCE and SYNOPSYS EDA tools . 1. GENUS & DESIGN COMPILER (Logic Synthesis) 2. INNOVUS & ICC (Place and Route) 3. QRC extraction (Parasitics Extraction) 4. TEMPUS & PRIME TIME (Signoff Timing Analysis) 5. PRIMETIME GCA - Constraints Analysis 6. SPYGLASS - Constraints Verification 7. CALIBRE - Mentor Graphics (Physical Verification) 8. VIRTUOSO (Analog Layout) . I have a good knowledge on Synthesis, Constraints Development, Constraints Verification, No Clock Analysis, Unconstrained Endpoint Analysis, Place And Route , Floor Planning , CTS , Routing ,DRC fixing , DRV fixing,Xtalk, Setup time and Hold time fixing, Static Timing Analysis, ECO FLOW...etc I have 2+ years experience on embedded hardware and firmware testing process. I have good knowledge on PCB trouble shoot.