• 6 Years of experience in backend physical design, Tools , flows and methodology (TFM). This includes new feature enablement, codebase update and maintenance and pioneering new features working closely with the EDA tool vendors. • Worked on multiple successful tape-outs as a physical design engineer in Intel PSG group (FPGA group). Worked on signoff power measurement, timing constraints validation and RV/timing signoff tasks. • Five years of research experience in LDPC Decoding algorithms, fault and process tolerant circuit design with a good track record of peer reviewed publications. • Author of 10+ patents/papers/book chapter in IEEE and conferences in the field of fault tolerance and error correction with more than 150+ total citations (source: Google Scholar). • Excellent team player with good organizational and communication skills.