About me

Proficient in VHDL/Verilog & Xilinx FPGAs/ASIC. • Microblaze and Zynq SOC based processor subsystem creation for Xilinx FPGAs . ASIC design flow and synopsys tools Spyglass VCS . Lint, CDC,RDC and timing closure and sign off .FuSa(functional safety)feature implementation for automotive design, DFA and DFMEA document • FPGA development flow: micro-architecting, RTL coding, Synthesis & implementation flow, verification and validation. • Interact with SW and HW teams to deliver the product to the clients • RTL Design, synthesis, static timing analysis(STA) and clock domain crossing(CDC) • On-chip debugging of FPGA designs using Vivado hardware debug tool • Modeling the algorithms in Octave/MATLAB, generating test vectors, visualizing data. • Familiarity with Xilinx IP cores and customization options : UART, IIC, AXI, QSPI etc., • Board bring up and validation with test RTL and TCL Script. • Familiarity with scripting languages like TCL and PERL • Familiarity with System verilog • Experience in communication interfaces like AXI, UART, IIC, SPI, RIO etc