(i) 1 year of experience at NXP as RTL Synthesis & Physical Design Engineer Intern in Radio Frequency Processing SoC Team. Worked on PPA (Power Performance Area) of a Block, generated Gate Level Netlist from input RTL design and done LEC, Power Estimation & Physical Design on latest technology node. EDA Tools : Cadence Genus, Cadence Innovus, Cadence Conformal, Ansys-PowerArtist & Simvision. (ii) 1+ years of experience in doing Computer Vision research at DSP Lab, IIT Patna. Worked on latest topics of Computer Vision like: Image Super-Resolution, Image Denoising, Image Restoration, Text to Image Generation (CLIP) & Image Contrast Enhancement. Our Lab group got research paper published in top conference of the world: IEEE/CVF Computer Vision & Pattern Recognition (CVPR) 2024. Paper Name: CFAT - Unleashing Triangular Window for Single Image Super-Resolution.