• 8+ years of experience in physical design (RTL to GDS) and Taped In multiple projects and also developed multiple automation flows/Automation tools in back end design. • Good in fixing toughest setup/hold problems even after automated fixing capabilities of EDA tools are exhausted. • Experience of going through multiple testchips/production tapeouts at latest nm • Experience of analyzing/resolving issues based on silicon feedback. • Hands on experience and in depth knowledge of full chip and block level ASIC design flow from synthesis to GDSII, involving deep submicron effects related to crosstalk/SI/glitch, metal fill, OCV/AOCV, process/voltage/temperature corners and power • Expert in identifying automation opportunities, and using various scripting languages (tcl, Python, tK,PERL,csh ad java frame work) on the fly to streamline/simplify repetitive tasks involving analysis/fixing violations and generate/parse/summarize useful reports and developed an automation to name called Streamliner in IINTEL. • Enjoys tough challenges, new learning opportunities and solving difficult problems • Experienced at leading and collaborating with different teams across different geographies Specialties: • Tools: FC Compiler,IC compiler, PrimeTime SI, StarRC, Design Compiler, Formality, Redhawk , Innovus and tempus • Languages/Scripts: Tcl, Python, Perl, awk, sed, C shell/Make, Java, C++, Verilog, Tk I have started a NGO called "SAAHASAM". from which I want to give better education for village children s. We are working on rural educational development.