I am a research-driven software engineer specializing in computer systems, EDA, and formal verification. With a B.Tech in Computer Science (DGPA: 8.82) and AIR 43 in GATE CS/IT 2019, I have a strong foundation in compiler optimizations, HDL parsing, and high-performance computing. At Verific Design Automation, I developed EDA tools and scalable architectures, collaborating with top semiconductor companies. My expertise lies in C++, SystemVerilog, and formal methods for hardware verification. Passionate about bridging software, hardware, and formal verification, I am open to research collaborations and next-gen computing innovations.