Skills - Experienced in designing AI-chip using memory-computing (using NOR-flash cell) from Analog Inference (3-years) - Experience in designing 3D-NAND Flash Memory (3-bits/cell, 4-bits/cell and 5-bits/cell) from Intel (4-years) - Experienced in mixed-signal design simulation and modeling - Experienced in modeling and simulation of:  FCXA: fully spice environment  FC AMS: Digital TB + spice netlist (Analog) + RTL (logical blocks)  FC AMS FT: Digital TB + spice netlist (Analog) + spice netlist (logical block) - Familiar with analog design methodology, EDA tools, CAD tools, and design, simulation, layout, and verification tools  Synopsys, Cadence, Mentor Graphics - Expert with Virtuoso Analog Design Environment: ADE-Explorer/Assembler/L/XL/GXL - Familiar with ADE usage for post-layout simulation. Use the + post layout option to include SPF files in ADE Explorer which will enhance performance and accuracy. Use the hierarchy editor's SPF view. For post-layout simulation, use the extracted view (av extracted: to re-annotate parasitic properties onto a layout design) - Familiar with ADE Assembler usage for parameterize cell views through the configuration view - Familiar with ADE Assembler usage for verification - Familiar with Simulink, MATLAB, Synopsys Tools, PSpice, Verilog, Cadence Virtuoso, VHDL, Data Structures