Hi. Myself Dipak Bhapkar, working as a Synthesis and STA Engineer at Analog Devices since November 2020. In this role, I have gained hands-on experience in block-level synthesis, focusing on data path optimization and constraint development. I have also dealt with timing-critical blocks and successfully performed block level & full-chip STA on technology nodes like 28nm, 22nm and 16nm. One of my significant projects involved complete ownership of the synthesis and STA of two blocks, where I implemented iSpatial flow for a timing-critical block, leading to improved QoR. Additionally, I worked on functional and scan STA at the block and top level, using AOCV methodology and constraint development. To streamline the process, I developed TCL, python scripts for timing violation analysis, DRV and, noise reports. I was the co-author in a paper on "Timing closure and implementation challenges" presented at ADI's global technical conference 2023. During M.Tech, I have also presented paper at the IEEE 3rd International Conference on Energy, Power, and Environment related to the field of Clean Energy Technologies. In addition to my technical skills, I am proficient in C, Tcl, and Python languages, and have hands-on experience with Cadence tools like Genus, Tempus, and Virtuoso. As a part of my courswork during M.Tech I have studied Analog & Digital VLSI Circuits and Mixed Signal Circuits, and also served as a Teaching Assistant, guiding and evaluating my junior peers in lab assignments, quizzes, and examination papers. Notably, I achieved an All India Rank of 172 in GATE-2018 and completed Cadence's badge exam courses on synthesis using Genus tool & timing analysis using Tempus tool.