✔️Responsible for development of layout for various IP's from LEF to GDSII deliverables. ✔️Blocks to name LVDS, PLL,Modulators,Deserializers,POR,LDO,OTA,Rx-Comparators and many more ✔️Adept in floorplanning,power planning,placement,routing ,top-level integration and physical verification ✔️Having hands on experience in Place &Route , STA ✔️Understanding the design and taking layout decisions to meet the spec ✔️Hands on experience in layout automation and developing methodology Tools - Cadence Virtuoso,Siemens Calibre RVE, Cadence Innovus ,Synopsys -PT Scripting - SKILL,Python Interests- 🖋️Analog Layout 🖋️ EDA 🖋️Semiconductor Device Physics 🖋️ Photography To know or discuss more on layouts drop a "Hi" to my mailbox,Happy to Respond :)