About me

Dhanush is currently working as Senior Silicon Design Engineer at AMD. He has 7.5 years of industry experience in DFT and ATE, including ATPG, test coverage debug, timing simulations on gate level netlist, spyglass analysis and silicon bring up, with familiarity in Emulation He has cracked interviews in some of the top-tier semiconductor companies like 𝗔𝗠𝗗, 𝗜𝗻𝘁𝗲𝗹, 𝗤𝘂𝗮𝗹𝗰𝗼𝗺𝗺, 𝗠𝗲𝗱𝗶𝗮𝗧𝗲𝗸 and many service companies. ➡️ Are you a fresh grad out of college, who's in a dilemma about your career in VLSI? ➡️ Are you a VLSI enthusiast, trying to make a career in it? ➡️ Are you trying to switch to a different domain in VLSI? ➡️ Want to be a stand out candidate, when you apply for that dream job? ➡️ Do you second guess your CV/resume and need a professional advise? ➡️ Do you have an interview lined up and need a mock interview session? ➡️ Do you lowball yourself, when it comes to salary negotiation? ➡️ Do you have what it takes, to crack an interview in a product based company? Why connect with Dhanush? 👨‍💻 ➡️ Having cleared interviews at top-tier semiconductor companies, he has a niche idea of what is expected in VLSI industry.💼 ➡️ He's one of the regular interview panel members at his organization and has interviewed a number of candidates.🎙️ Major highlights: Awarded with "GCX Next 5% Award" for First Time Right ATPG Patterns at AMD, Q2 2024. Awarded with "Executive Spotlight Award" for DFT Quality Enhancements at AMD, Q3 2023. Awarded with "EPG SiE Award" for achieving closure on showstopper power sightings to ungate tapeout at Intel, Q4 2021. Dhanush is happy to guide you and give his two cents. Don't hesitate to reach out if you have any questions or just want to say hi! DISCLAIMER: All activities on this platform represents solely my own opinions and is not in any way, shape, or form, a representation of my current or past employers.