About me

Dhanush currently serves as a Silicon Design Engineer at AMD, with 8+ years of extensive industry experience in Design for Test (DFT) and Automatic Test Equipment (ATE). His expertise spans ATPG, test coverage debugging, gate-level netlist timing simulations, Spyglass analysis, silicon bring-up, and emulation. Dhanush has successfully navigated interviews at several top-tier semiconductor companies, including AMD, Intel, Qualcomm, MediaTek, and various service-oriented organizations. ➡️Are you a recent graduate unsure about your career path in VLSI? ➡️Are you passionate about VLSI and seeking to break into the field? ➡️Are you looking to transition to a different domain within VLSI? ➡️Want to stand out as a strong candidate for your dream job? ➡️Need professional advice on optimizing your CV/resume? ➡️Preparing for an upcoming interview and in need of a mock session? ➡️Unsure about how to navigate salary negotiations? ➡️Want guidance on succeeding in interviews with top-tier product-based companies? Why Dhanush? 👨‍💻 ➡️With a successful track record in securing positions at top semiconductor companies, Dhanush has a niche idea of the expectations within the VLSI industry.💼 ➡️As a regular member of the interview panel at his organization, Dhanush has conducted numerous interviews, giving him valuable insights into what makes a candidate stand out.🎙️ Major highlights: Awarded "GCX Next 5% Award" for First Time Right ATPG Patterns at AMD, Q2 2024. Awarded "Executive Spotlight Award" for DFT Quality Enhancements at AMD, Q3 2023. Awarded "EPG SiE Award" for achieving closure on showstopper power sightings to ungate tapeout at Intel, Q4 2021. Dhanush is available to provide guidance, share insights, and offer advice tailored to your professional journey. Feel free to reach out with any questions or even just to connect! Disclaimer: All opinions and activities shared on this platform are solely those of Dhanush and do not represent the views or positions of any current or past employers.