VLSI & ASIC Career Mentorship — RTL to Tapeout

Are you breaking into VLSI, preparing for interviews, or navigating the ASIC design flow? I'm a Logic Design Engineer at IBM working on P11 processor silicon — I can help you with RTL design concepts, ASIC interview prep, M.Tech IIITD experience, and career guidance for roles in chip design.

Good for: Students targeting VLSI roles · RTL/verification interview prep · M.Tech admissions guidance · ASIC flow doubts (synthesis, STA, LEC, PD)