A DFT Engineer with a demonstrated history of working in the ASIC industry. Strong engineering professional with a BE - Bachelor of Engineering focused in Electronics and Communication from G H Patel College of Engineering & Technology. • Scan Insertion: Hierarchical Scan, CODEC, SPC Chain, Test Point insertion, Clock Delay Adjustment logic insertion, Core Wrapping (Intest-Extest), OCC Configuration, DRC fixes, Defining & Configuring various test modes. • Test Pattern Generation: ATPG at block & Top-level, DRC fixes, Coverage analysis & improvement, Stuck-at (SAF), Transition (TDF), Path Delay, IddQ fault model. • Simulation: Timing & w/o timing simulations • Post-silicon Validation: Pattern failure debug on ATE, Diagnosis, Masking, Netlist Independent Flow. • BIST: MBIST with Tessent LV Flow at the block level. • SDC generation & DFT Timing closer: Shift and Capture SDC generation • Logic Equivalence Checking • Spyglass checks