What Sets Me Apart: Passionate about ensuring design correctness through formal verification techniques, with expertise in assertion-based verification and property development.Skilled in verifying complex RTL designs to achieve bug-free, high-quality designs and first-pass success. 🔗 Want to Crack your Formal Verification Interviews, lets get in touch ? Technical Skills: 👨‍💻 Expert in building formal testbenches using Jasper and SystemVerilog Assertions (SVA) 📚 Skilled in abstraction techniques (Smart Tracker) for verifying IPs 🚀 Passionate about improving design quality with formal-first approaches Professional Highlights: 🛠️ 5+ years of experience in formal verification of complex IPs and Blocks ✅ Achieved sign-off using coverage on Power Cluster sub-block of CPU 🐞 Detected key corner-case bugs test chip missed by simulation Let’s Connect: 🤝 Want to discuss advanced formal techniques or collaborate on verification strategies?