I'm a Design Verification Engineer with 4+ years of experience building robust, coverage-driven verification solutions for complex SoC and IP designs. Currently at UST Global, I focus on AMBA AXI/AHB/APB protocols and system-level verification, including interconnect behavior, AXI transactions, and protocol compliance. Previously, I spent 4 years at Cadence Design Systems as a Sr. Validation Engineer, where I designed UVM-based testbenches, developed SystemVerilog testcases for feature-level validation, and led regression analysis and root cause debugging for Xcelium product releases. I'm passionate about functional verification, assertion-based methodologies, and mentoring engineers looking to break into the VLSI/DV domain — from SystemVerilog and UVM fundamentals to real-world debugging and regression workflows. Let's connect if you want guidance on DV career paths, interview prep, or hands-on verification concepts.