With over 13 years of experience in the semiconductor industry, I am a Verification Specialist at Microsoft, where I apply my expertise in ASIC verification to ensure the quality and performance of complex system-on-chip (SoC) and intellectual property (IP) designs. I work with leading-edge technologies and methodologies to verify the functionality, performance, and security of the SoC and IP products. My core competencies include verification languages such as System Verilog and UVM, verification methodologies such as OVM and UVM, verification protocols such as USB and AMBA, and verification tools such as Synopsys and Cadence. I have also adopted advanced verification techniques for some of the ASIC designs, such as Fabric interconnect verification, Navigation IP verification, and Security IP verification. In addition, I have led and managed a team of engineers on these verification projects, demonstrating my leadership and collaboration skills. I am interested in gaining more in-depth knowledge of the state-of-the-art technologies used for modern day ASIC verification and top-level verification, as well as expanding my domain expertise to other areas such as embedded systems and artificial intelligence. I am motivated by the challenge and satisfaction of delivering high-quality and reliable products that meet the needs and expectations of the customers. I am also passionate about photography and travel, and I enjoy exploring new places and cultures. Participated in DVCon India 2019 and got 1st position in Poster ‘SoC Verification Enablement Using HM Model’ Link to paper: https://dvcon-proceedings.org/document/soc-verification-enablement-using-hm-model-paper/