Experienced Synthesis and STA Engineer working on 7nm Finfet technology for automotive SOCs. Core competencies ranging from logical synthesis , STA , formal verification, automation using TCL , shell scripting , hand off checks development .Timing closure , constraints promotion , formal verification are my forte and areas where my exposure has been high. Eco flows and sound basic knowledge of DFT and Backend implementation flows makes my work synergic with other teams throughout the RTL to GDS flow. Core member of a team that designed the first 7nm chip for level 5 automotive driving ( now the best in its segment). Also won the Team Awesome award as an organisation level recognition. I am a highly motivated and enthusiastic VLSI design engineer with strong academic background . Stood 7th in my class of 196 in ECE (batch of 2017 ) at Delhi Technological University (DCE)