A Passionate VLSI Engineer with 3+ years of experience in Design Verification in IP and SOC level environment. # Strong Command on System Verilog and UVM || AMBA protocols. # Experienced in IP Verification || [PCIe] (2+ years). # Experience in SOC verification || Ethernet-800G (1+years). # Good Knowledge in Linux and GVIM editor. # Knowledge in repository like Github and version management tools DesignSync [DSSC].