Have: - Work experience on 28nm, and 32nm technology nodes - Practical hands on experience on Synthesis flow, Physical Design flow ,PV & STA signoff - understanding Floorplan , Powerplan , placement , routing , timing fixes and signoff checks - STA, TCL & Physical Design certification courses from takshila Institue of VLSI - Languages are known: Shell scripting, TCL,Perl, python - Tools: Synopsys ICC2, Cadence Innovas ,primetime, Tempus,dc_shell, Genus, pt_shell,starrc,ICV