A skilled RTL Design Engineer with nearly 3+ years of experience in the RTL design and verification domain. My expertise lies in RTL logic design using system Verilog, CDC and lint checks, static timing analysis. Throughout my career, I have gained an in-depth knowledge in RTL design and verification, utilizing a wide range of tools and methodologies such as System Verilog, VCS, Design compiler, PrimeTime, Virtuoso, Python scripting and coverage-based random constraint simulation. In addition to my technical skills, I have good communication skills and teamwork abilities. Highly motivated and committed to delivering high-quality design in stringent timelines.