Currenly Working in ASIC Implementation team at Kinara ai. Responsibilities includes synthesis, lec, clp, power and sta. Hands on Experience on writing synthesis constraints, hierarchical synthesis, mmmc flow and spatial synthesis and low power synthesis. Hands on Experience on Equivalent Checks and power analysis usign cadence tools. Hands on Experience on multi voltage designs using UPF and low power checks on post synthesis netlist. Experience on debugging the check timing issues in sta tool and developed the flows for dmmc for post layout sta, created view definition file for all corners and modes. Working knowledge on python and tcl scripting. Automated the flows using python. Completed masters from Bits Pilani Goa in the field of Microelectronics in 2020. Good understanding of Digital Design, VLSI, Physical design, STA, Synthesis. Skills - Verilog, TCL scripting, shell scipting, python, Digital Design, Physical design, Static timing analysis.