I’m an enthusiastic RTL Design Engineer with a strong foundation in Digital Design, Verilog, and FPGA development. My experience spans from building 32-bit RISC-V and MIPS processors to implementing verification flows using UVM. I’ve worked with tools like Xilinx Vivado, Cadence, QuestaSim, and Synopsys in academic and internship projects. Beyond just technical skills, I enjoy mentoring others — helping them debug their HDL code, build solid project portfolios, confidently face interviews. I believe with the right guidance and consistency, anyone can break into the VLSI industry, regardless of their college background. If you're working on a project, confused about your next step, or simply need a push in the right direction — let’s connect.