“Always in learning mode. Always debugging something.” Hi, I’m Bharath — a Physical Design Engineer experienced in RTL-to-GDSII flow with hands-on experience in floorplanning, placement, clock tree synthesis, and routing. And driven by the urge to build silicon that’s fast, reliable, and beautiful in layout. I'm learning every day — from understanding clock tree topology and skew tuning to digging into parasitic delay paths. Tools like Design Compiler, Innovus & PrimeTime are my playgrounds, but my real weapon? Curiosity. If you’re someone who sees floorplanning as strategy, timing as logic, and debugging as meditation — let’s connect. I’d love to learn from you or share what I know.