I’m an Electronics and Communication Engineering student with a strong focus on VLSI and digital design. I am passionate about RTL design, FPGA development, and semiconductor innovation. With hands-on experience in Verilog, SystemVerilog, and tools like Xilinx ISE and Quartus Prime, I enjoy turning complex design problems into optimized hardware solutions. I’m particularly drawn to front-end design and verification, and I'm constantly exploring new ways to sharpen my skills in digital logic, scripting (TCL, Python), and verification methodologies. 🔍 What drives me: Continuous learning, collaborative problem-solving, and building silicon systems that power tomorrow’s technology. 🔧 Skills & Interests: • RTL Design (Verilog, SystemVerilog, UVM) • FPGA/ASIC Design & Prototyping • Scripting (TCL, Python) • Digital Electronics & CMOS Fundamentals • Verification & Functional Simulation 📈 I’m open to opportunities in VLSI design, front-end verification, and digital hardware roles where I can grow and contribute to cutting-edge innovation.